The present invention relates generally to computer flash memory systems, and more particularly to systems and methods for improving the gate coupling in flash memory elements.
Computer non-volatile (flash) memory chips such as electrically programmable read only memory (EPROM) chips are used in many applications, including hand held computing devices, wireless telephones, and digital cameras. In computer flash memory, a flash memory core containing a matrix of memory elements is surrounded by a periphery containing peripheral elements. The elements in the core assume physical states which represent bits of data. Consequently, by configuring the core elements appropriately, data (such as preselected telephone numbers in a wireless telephone or digital images in a digital camera) may be stored in the core and subsequently read by detecting the physical state of one or more core elements.
To enable the individual memory elements of a flash memory chip to maintain the physical state with which they have been programmed, each element must be isolated from its neighboring elements. In the case of the peripheral elements, isolation is achieved by a method referred to in the art as local oxidation silicon, or xe2x80x9cLOCOSxe2x80x9d. LOCOS isolation requires disposing a silicon oxide insulator between neighboring elements. While acceptable for isolating peripheral elements, however, LOCOS isolation is less than desirable for core element isolation. This is because it is desirable to minimize the distance between core elements to increase memory density, and the silicon in LOCOS isolation tends to encroach on the core memory elements, thereby decreasing core element (and, hence, memory) density.
Accordingly, a process that renders closely spaced memory core elements, referred to in the art as xe2x80x9cself-alignedxe2x80x9d elements, has been developed. Self-aligned memory core elements are isolated from each other by shallow trenches that are etched into the silicon substrate of the core, between adjacent memory elements.
The memory elements between the trenches are established by one or more layers of polysilicon material, with the layers being aligned with each other and not overlapping the trenches. As recognized herein, two layers of polysilicon can be used in floating gate EPROM flash memory, with the use of two layers facilitating individual doping of each layer, thereby providing finer control of the doping of each memory element as compared to memory elements having only a single layer of polysilicon. When two layers of polysilicon material are to be used, an interpoly dielectric material is sandwiched between the two to separate the polysilicon layers. The top most polysilicon layer establishes a control gate for the memory element.
Regardless of the number of polysilicon layers used, the polysilicon material ordinarily used in flash memory is made of relatively small grained crystals. Indeed, the use of a type of large grained polysilicon material known as hemispherical-grained (HSG) polysilicon is avoided. This is because HSG polysilicon in the past has generally considered to be of insufficient quality for EPROM flash memory applications.
Nevertheless, in a paper entitled xe2x80x9cA 0.54 xcexcm2 Self-Aligned, HSG Floating Gate Cell (SAHF Cell) for 256 Mbit Flash Memoriesxe2x80x9d by Shirai et al. (IEDM 95-653, published by IEEE) (hereinafter xe2x80x9cShirai et al.xe2x80x9d) a flash memory having a single layer of polysilicon material made of HSG is disclosed for improving gate coupling. Thus, as taught in Shirai et al., the conventional small-grained polysilicon layer that establishes the floating gate of the memory element is eliminated and replaced with an HSG structure.
As recognized by the present invention, however, the large, irregularly-shaped grains taught by Shirai et al. do not establish a relatively flat, smooth bottom surface (i.e., the surface oriented toward the silicon substrate of the chip). This is unfortunate, because the bottom surface of a floating gate polysilicon layer must be positioned flush against a very thin tunnel oxide layer that is grown on the silicon substrate of the memory chip. Otherwise, the present invention understands that the tunnel oxide layer undesirably can be influenced by the HSG during subsequent thermal steps. Indeed, the single HSG layer of Shirai et al. diminishes the performance of the memory chip grain growth. Fortunately, as recognized by the present invention, an HSG polysilicon layer can be used in a flash memory device to improve gate coupling while providing for a flat, smooth interface between a tunnel oxide layer and a polysilicon layer.
Accordingly, it is an object of the present invention to provide a method and system for facilitating gate coupling in memory elements of a computer flash memory device. Another object of the present invention is to provide a method and system for facilitating gate coupling in memory elements of a computer flash memory device which establishes a relatively flat, smooth interface between a tunnel oxide layer in the device and a polysilicon layer in the device. Still another object of the present invention is to provide a method and system for facilitating gate coupling in memory elements of a computer flash memory device that is easy to use and cost effective.
A process is disclosed for making a flash memory core. The process includes the steps of providing at least one silicon substrate and establishing plural stacks on the substrate. Each stack is positioned over a tunnel oxide layer that faces the substrate, and each stack includes at least one polysilicon layer above the tunnel oxide layer. At least one hemispherical-grained (HSG) layer is established above the polysilicon layer.
In one preferred embodiment, the step of establishing at least one HSG layer includes depositing the polysilicon layer on the tunnel oxide, and then depositing the HSG layer on the polysilicon layer. Next, the HSG layer is etched to partially overlap insulative material in isolation trenches. Then, an interpoly dielectric layer and a polysilicon xe2x80x9c2xe2x80x9d layer are deposited above the HSG layer to establish a control gate.
If desired, the method can further include forming isolation trenches between at least two stacks and forming at least one sidewall layer on at least some of the stacks. The sidewall layers protects the tunnel oxide during dry etching. The stacks can be self-aligned memory element stacks, in which case each stack can include the polysilicon layer on the tunnel oxide, a high temperature oxide layer on the polysilicon layer, and a nitride layer on the high temperature oxide layer.
Preferably, the method additionally includes disposing an insulative material in at least some of the trenches prior to the step of establishing at least one HSG layer. Furthermore, the preferred method includes the steps of polishing the insulative material down to the polysilicon layer, and, during the polishing step, removing the nitride layer and the high temperature oxide layer. A flash memory wafer made according to the present method, as well as a computing device incorporating the flash memory wafer, are also disclosed.
In another aspect of the present invention, a flash memory wafer includes a core memory region including at least one silicon substrate. Also, the flash memory wafer includes plural stacks in the core memory region, with each stack having at least one respective polysilicon layer on a tunnel oxide layer and at least one HSG layer above the polysilicon layer.
In still another aspect, a method for making a flash memory wafer includes establishing plural stacks on at least one silicon substrate. A tunnel oxide layer is disposed between each stack and the substrate, and each stack includes at least one polysilicon layer on the tunnel oxide layer. The method further contemplates establishing at least one HSG layer above the polysilicon layer in at least some of the stacks.
Other features of the present invention are disclosed or apparent in the section entitled: xe2x80x9cDETAILED DESCRIPTION OF THE INVENTIONxe2x80x9d.